Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test

ABSTRACT

A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N&gt;1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.

RELATED APPLICATION DATA

[0001] This application claims the benefit of U.S. ProvisionalApplication No. 60/268,601 filed Feb. 15, 2001, which is herebyincorporated by reference.

TECHNICAL FIELD

[0002] The present invention generally relates to the testing of logicdesigns in an integrated circuit or circuit assembly embedded withdesign-for-test (DFT) techniques. Specifically, the present inventionrelates to the detection or location of logic faults within each clockdomain and logic faults crossing any two clock domains, during self-testor scan-test, in an integrated circuit or circuit assembly.

BACKGROUND OF THE INVENTION

[0003] In this specification, the term integrated circuit is used todescribe a chip or MCM (multi-chip module) embedded with design-for-test(DFT) techniques. The terms circuit assembly and printed circuit boardwill be considered interchangeable. The term circuit assembly includesprinted circuit boards as well as other types of circuit assemblies. Acircuit assembly is a combination of integrated circuits. The resultingcombination is manufactured to form a physical or functional unit.

[0004] An integrated circuit or circuit assembly, in general, containstwo or more systems clocks, each controlling one module or logic block,called clock domain. Each system clock is either directly coming from aprimary input (edge pin/connector) or generated internally. These systemclocks can operate at totally unrelated frequencies (clock speeds), atsub-multiples of each other, at the same frequency but with differentclock skews, or at a mix of the above. Due to clock skews among thesesystem clocks, when a DFT technique, such as self-test or scan-test, isemployed, it is very likely that faults associated with the functionbetween two clock domains, called crossing clock-domain faults, willbecome difficult to test. In the worst case, these crossing clock-domainfaults when propagating into the receiving clock domain could completelyblock detection or location of all faults within that clock domain.Thus, in order to solve the fault propagation problem, DFT approachesare proposed to take over control of all system clocks and reconfigurethem as capture clocks.

[0005] Prior-art DFT approaches in this area to testing crossingclock-domain faults as well as faults within each clock domain centeredon using the isolated DFT, ratio'ed DFT, and one-hot DFT techniques.They are all referred to as single-capture DFT techniques, because noneof them can provide multiple skewed capture clocks (or an orderedsequence of capture clocks) in each capture cycle during self-test orscan-test.

[0006] In using the isolated DFT technique, all boundary signalscrossing a clock domain and flowing into the receiving clock domains arecompletely blocked or disabled by forcing each of them to apredetermined logic value of 0 or 1. See U.S. Pat. No. 6,327,684 issuedto Nadeau-Dostie et al. (2001). This approach, in general, can allow allclock domains to be tested in parallel. The major drawbacks of thisapproach are that it requires insertion of capture-disabled logic inbetween clock domains and all scan enable signals each associated withone clock domain must be operated at-speed. The design change could takesignificant efforts and it might impact normal mode operation. Runningall scan enable signals at-speed requires routing them as clock signalsusing layout clock-tree synthesis (CTS). In addition, since boundarysignals can traverse through two clock domains in both directions, thisapproach requires testing crossing clock-domain faults in two or moretest sessions. This could substantially increase the test time requiredand might make the capture-disabled logic even more complex to implementthan anticipated.

[0007] In using the ratio'ed DFT technique, all clock domains must beoperated at sub-multiples of one reference clock. For instance, assumethat a design contains 3 clock domains running at 150 MHz, 80 MHz, and45 MHz, respectively. The 3 clock domains may have to be operated at 150MHz, 75 MHz, and 37.5 MHz during testing. See U.S. Pat. No. 5,349,587issued to Nadeau-Dostie et al. (1994). This approach reduces thecomplexity of testing a multiple-frequency design and avoids potentialraces or timing violations crossing clock domains. It can also allowtesting of all clock domains in parallel. However, due to changes inclock-domain operating frequencies, this approach loses its self-test orscan-test intent of testing multiple-frequency designs at their ratedclock speeds (at-speed) and may require significant design and layoutefforts on re-timing (or synchronizing) all clock domains. Powerconsumption could be also another serious problem because all scan cells(memory elements) are triggered simultaneously every few cycles.

[0008] In using the one-shot DFT technique, each crossing clock-domainsignal flowing into its receiving clock domains must be initialized toor held at a predetermined logic value of 0 or 1 first. Thisinitialization is usually accomplished by shifting in predeterminedlogic values to all clock domains so that all crossing clock-domainsignals are forced to a known state. Testing is then conducteddomain-by-domain, thus, called one-hot testing. See U.S. Pat. No.5,680,543 issued to Bhawmik et al. (1997). The major benefits of usingthis approach are that it can still detect or locate crossingclock-domain faults and does not need insertion of disabled logic, inparticular, in critical paths crossing clock domains. However, unlikethe isolated or ratio'ed DFT approach, this approach requires testing ofall clock domains in series, resulting in long test time. It alsorequires significant design and layout efforts on re-timing (orsynchronizing) all clock domains.

[0009] Two additional prior-art DFT approaches had also been proposed,one for scan-test, the other for self-test. Both approaches are referredto as multiple-capture DFT techniques, because they can provide multipleskewed capture clocks (or an ordered sequence of capture clocks) in eachcapture cycle during scan-test or self-test.

[0010] The first prior-art multiple-capture DFT approach is to testfaults within each clock domain and faults between two clock domains inscan-test mode. See U.S. Pat. No. 6,070,260 issued to Buch et al. (2000)and U.S. Pat. No. 6,195,776 issued to Ruiz et al. (2001). Theseapproaches rest on using multiple skewed scan clocks or multiple skewcapture events each operating at the same reduced clock speed in an ATE(automatic test equipment) to detect faults. Combinational ATPG(automatic test pattern generation) is used to generate scan-testpatterns and ATE test programs are created to detect faults in theintegrated circuit. Unfortunately, currently available ATPG tools onlyassume the application of one clock pulse (clock cycle) to each clockdomain. Thus, these approaches can only detect stuck-at faults inscan-test mode. No prior art using multiple skewed capture clocks wereproposed to test delay or stuck-at faults requiring two or more captureclock pulses for full-scan or partial-scan designs.

[0011] The second prior-art multiple-capture DFT approach is to testfaults within each clock domain and faults between two clock domains inself-test mode. See the paper co-authored by Hetherington et al. (1999).This approach rests on using multiple shift-followed-by-capture clockseach operating at its operating frequency, in a programmable capturewindow, to detect faults at-speed. It requires clock suppression,complex scan enable (SE) timing waveforms, and shift clock pulses in thecapture window to control the capture operation. These shift clockpulses may also need precise timing alignment. As a result, it becomesquite difficult to perform at-speed self-test for designs containingclock domains operated at totally unrelated frequencies, e.g., 133 MHzand 60 MHz.

[0012] Thus, there is a need for an improved method, apparatus, orcomputer-aided design (CAD) system that allows at-speed or slow-speedtesting of faults within clock domains and between any two clock domainsusing a simple multiple-capture DFT technique. The method and apparatusof the present invention will control the multiple-capture operations ofthe capture clocks in self-test or scan-test mode. It does not requireusing shift clock pulses in the capture window, insertingcapture-disabled logic in normal mode, applying clock suppression oncapture clock pulses, and programming complex timing waveforms on scanenable (SE) signals. In addition, the CAD system of the presentinvention further comprises the computer-implemented steps of performingmultiple-capture self-test or scan synthesis, combinational faultsimulation, and combinational ATPG that are currently unavailable in theCAD field using multiple-capture DFT techniques.

SUMMARY OF THE INVENTION

[0013] Accordingly, a primary objective of the present invention is toprovide an improved multiple-capture DFT system implementing themultiple-capture DFT technique. Such a DFT system will comprise a methodor apparatus for allowing at-speed/slow-speed detection or location offaults within all clock domains and faults crossing clock domains in anintegrated circuit or circuit assembly. In the present invention, themethod or apparatus can be realized and placed inside or external to theintegrated circuit or circuit assembly.

[0014] A computer-aided design (CAD) system that synthesizes such a DFTsystem and generates desired HDL test benches and ATE test programs isalso included in the present invention. A hardware description language(HDL) is used to represent the integrated circuit includes, but is notlimited to, Verilog or VHDL. An ATE is an IC tester or any equipmentthat realizes the multiple-capture DFT system and is external to theintegrated circuit or circuit assembly under test.

[0015] The present invention focuses on multiple-capture DFT systems forself-test and scan-test. In a self-test environment, a self-test cycleoften comprises 3 major operations: shift, capture, and compact. Theshift and compact operations can occur concurrently during eachself-test cycle. In order to increase the circuit's fault coverage, itis often necessary to include scan-test cycles to perform top-up ATPG. Ascan-test cycle often comprises 3 major operations in a scan-testenvironment: shift, capture, and compare. The shift and compareoperations can occur concurrently during each scan-test cycle. In amixed self-test and scan-test environment, the scan-test cycle mayexecute a compact operation rather than the compare operation. Thus, inthe present invention, a self-test cycle further comprises the shift,capture, and compare operations, and a scan-test cycle further comprisesthe shift, capture, and compact operations.

[0016] The multiple-capture DFT system of the present invention furthercomprises any method or apparatus for executing the shift and compact orshift and compare operations concurrently during each self-test orscan-test cycle. It is applicable to test any integrated circuit orcircuit assembly which contains N clock domains, where N>1. Each captureclock controls one clock domain and can operate at its rated clock speed(at-speed) or at a reduced clock speed (slow-speed), when desired.

[0017] During the shift operation, the multiple-capture DFT system firstgenerates and shifts in (loads) N pseudorandom or predetermined stimulito all scan cells within all clock domains, concurrently. The shiftingfrequency is irrelevant to at-speed testing. Depending on needs, aslower frequency can be used to reduce power consumption and a fasterfrequency can be used to reduce the test application time. Themultiple-capture DFT system must wait until all stimuli have been loadedor shifted into all scan cells. By that time, all scan enable (SE)signals each associated with one clock domain shall switch from theshift operation to the capture operation. After the capture operation iscompleted, all scan enable (SE) signals shall switch from the captureoperation to the shift operation. One global scan enable (GSE) signalcan be simply used to drive these scan enable signals.

[0018] The multiple-capture DFT system of the present invention furthercomprises any method or apparatus for performing the shift operation atany selected clock speed within each clock domain and using only oneglobal scan enable (GSE) signal to drive all scan enable (SE) signalsfor at-speed or slow-speed testing. The GSE signal can be also operatedat its selected reduced clock speed. Thus, there is no need to routethese SE signals as clock signals using layout clock tree synthesis(CTS). This invention applies to any self-test or scan-test method thatrequires multiple capture clock pulses (without including shift clockpulses) in the capture cycle.

[0019] After the shift operation is completed, an ordered sequence ofcapture clocks is applied to all clock domains. During the captureoperation, each ordered sequence contains N capture clocks of which onlyone or a few will be active at one time. There are no shift clock pulsespresent within each capture cycle. Testing of delay faults at-speed isnow performed by applying two consecutive capture clock pulses (doublecaptures) rather than using the shift-followed-by-capture clock pulses.Performing multiple captures in the capture cycle reduces the risk ofdelay test invalidation and false paths that might occur due to illegalstates in scan cells resulting from filling them with pseudorandom orpredetermined stimuli.

[0020] In the present invention, the multiple-capture DFT system uses adaisy-chain clock-triggering or token-ring clock-enabling technique togenerate and order capture clocks one after the other. One major benefitof using this approach is that the test results are repeatable no matterwhat clock speed will be used for each capture clock. The problem is itcould be difficult to precisely control the relative clock delay betweentwo adjacent capture clocks for testing delay faults between clockdomains.

[0021] As an example, assume that the capture cycle contains 4 captureclocks, CK1, CK2, CK3, and CK4. (Please refer to FIGS. 3 and 10 in theDETAILED DESCRIPTION OF THE DRAWINGS section for further descriptions).The daisy-chain clock-triggering technique implies that completion ofthe shift cycle triggers the GSE signal to switch from shift to capturecycle which in turn triggers CK1, the rising edge of the last CK1 pulsetriggers CK2, the rising edge of the last CK2 pulse triggers CK3, andthe rising edge of the last CK3 pulse triggers CK4. Finally, the risingedge of the last CK4 pulse triggers the GSE signal to switch fromcapture to shift cycle.

[0022] The token-ring clock-enabling technique implies that completionof the shift cycle enables the GSE signal to switch from shift tocapture cycle which in turn enables CK1, completion of CK1 pulsesenables CK2, completion of CK2 pulses enables CK3, and completion of CK3pulses enables CK4. Finally, completion of CK4 pulses enables the GSEsignal to switch from capture to shift cycle.

[0023] The only difference between these two techniques is that theformer uses clock edges to trigger the next operation, the latter usessignal levels to enable the next operation. In practice, a mixedapproach can be employed. Since a daisy-chain or token-ring approach isused, the multiple-capture DFT system allows testing of any frequencydomain at a reduced clock speed when this particular frequency domaincannot operate at-speed. This is very common in testing high-speedintegrated circuits, such as microprocessors and networking chips, wheredifferent clock speeds of chips are sold at different prices. Inaddition, due to its ease of control, this approach further allowsat-speed scan-test simply using internally reconfigured capture clocks.Thus, a low-cost tester (ATE) can be used for at-speed scan-test, inaddition to at-speed self-test.

[0024] The multiple-capture DFT system in the present invention furthercomprises applying an ordered sequence of capture clocks and operatingeach capture clock at its selected clock speed in the capture operation(cycle). The ordered sequence of capture clocks is applied to thecircuit under test one-by-one using the daisy-chain clock-triggering ortoken-ring clock-enabling technique. The order of these capture clocksis further programmable, when it's required to increase the circuit'sfault coverage. Each capture clock can be also disabled or chosen tofacilitate fault diagnosis. In addition, when two clock domains do notinteract with each other, they can be tested simultaneously to shortenthe capture cycle time.

[0025] Each capture clock of the present invention further comprises oneor more clock pulses. The number of clock pulses is furtherprogrammable. When self-test is employed, the multiple-capture DFTsystem is usually placed inside the integrated circuit and, thus, allcapture clocks are generated internally. When scan-test is employed, themultiple-capture DFT system is usually resided in an ATE and, thus, allcapture clocks are controlled externally. However, for at-speedscan-test, it's often required to capture output responses using itsrespective operating frequency within each clock domain. The presentinvention further comprises any method or apparatus for allowing use ofinternally-generated or externally-controlled capture clocks forat-speed scan-test or self-test.

[0026] After the capture operation is completed, all output responsescaptured at all scan cells are compacted internally to signatures orshifted out to the multiple-capture DFT system for direct comparison.The compact or compare operation occurs concurrently with the shiftoperation, and the process of shift, capture, and compact/compareoperations shall continue until a predetermined limiting criteria, suchas completion of all self-test or scan-test cycles, is reached. Finally,the multiple-capture DFT system will compare the signatures againstexpected signatures when the compact operation is employed duringself-test or scan-test. Such comparison can be done either in theintegrated circuit with a built-in comparator or in an ATE by shiftingthe final signatures out for analysis.

[0027] In the present invention, both self-test and scan-test techniquesare employed to detect or locate stuck-at and delay faults. The stuck-atfaults further comprise other stuck-type faults, such as open andbridging faults. The delay faults further comprise other non-stuck-typedelay faults, such as transition (gate-delay), multiple-cycle delay, andpath-delay faults. In addition, each scan cell can be a multiplexed Dflip-flop or a level sensitive latch, and the integrated circuit orcircuit assembly under test can be a full-scan or partial-scan design.

[0028] In general, it is only required to apply one clock pulse and twoconsecutive clock pulses to test stuck-at faults and delay faults withinone clock domain, respectively. Multiple-cycle paths present within oneclock domain and between clock domains, however, require waiting for anumber of clock cycles for capturing. To test multiple-cycle pathswithin clock domains, the present invention further comprise applyingonly one clock pulse to test these multiple-cycle paths within eachclock domain by reducing the frequency of that domain's capture clockspeed to the level where only paths of equal cycle latency (cycledelays) are captured at its intended rated clock speed one at a time. Totest multiple-cycle paths between two clock domains, the presentinvention further comprise adjusting the relative clock delay along thepaths to the level where the crossing-boundary multiple-cycle paths arecaptured at its intended rated clock speed.

[0029] To summarize, the present invention centers on using one globalscan enable (GSE) signal for driving all scan enable (SE) signals at areduced clock speed and applying an ordered sequence of capture clocksfor capturing output responses in both self-test and scan-test modes.The present invention assumes that the integrated circuit or circuitassembly must contain two or more clock domains each controlled by onecapture clock. During self-test, each capture clock shall contain one ormore clock pulses, and during scan-test, one of the capture clocks mustcontain two or more clock pulses.

[0030] Due to its ease of control on the scan enable and capture clocksignals, the multiple-capture DFT system of the present invention cannow be easily realized by an apparatus and synthesized usingcomputer-aided design (CAD) tools. The present invention furthercomprises such a CAD system for synthesizing the apparatus and verifyingits correctness using combinational fault simulation and combinationalATPG in self-test or scan-test mode.

BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other objects, advantages and features of theinvention will become more apparent when considered with the followingspecification and accompanying drawings wherein:

[0032]FIG. 1 shows an example full-scan or partial-scan design with 4clock domains and 4 system clocks, where a multiple-capture DFT systemin accordance with the present invention is used to detect or locatestuck-at faults at a reduced clock speed in self-test or scan-test mode.

[0033]FIG. 2 shows a multiple-capture DFT system with multiple PRPG-MISRpairs, in accordance with the present invention, which is used at areduced clock speed in self-test mode to detect or locate stuck-atfaults in the design given in FIG. 1.

[0034]FIG. 3 shows a timing diagram of the full-scan design given inFIG. 1, in accordance with the present invention, where an orderedsequence of capture clocks is used to detect or locate stuck-at faultswithin each clock domain and stuck-at faults crossing clock domains inself-test mode. The chain of control events is also shown.

[0035]FIG. 4 shows a timing diagram of the full-scan design given inFIG. 1, in accordance with the present invention, where a shortened yetordered sequence of capture clocks is used to detect or locate stuck-atfaults within each clock domain and stuck-at faults crossing clockdomains in self-test mode.

[0036]FIG. 5 shows a timing diagram of the full-scan design given inFIG. 1, in accordance with the present invention, where an expanded yetordered sequence of capture clocks is used to detect or locate otherstuck-type faults within each clock domain and other stuck-type faultscrossing clock domains in self-test or scan-test mode.

[0037]FIG. 6 shows a timing diagram of the partial-scan design given inFIG. 1, in accordance with the present invention, where an orderedsequence of capture clocks is used to detect or locate stuck-at faultswithin each clock domain and stuck-at faults crossing clock domains inself-test or scan-test mode.

[0038]FIG. 7 shows an example full-scan or partial-scan design with 4clock domains and 4 system clocks, where a multiple-capture DFT systemin accordance with the present invention is used to detect or locatestuck-at, delay, and multiple-cycle delay faults at its desired clockspeed in self-test or scan-test mode.

[0039]FIG. 8 shows a multiple-capture DFT system with multiple PRPG-MISRpairs, in accordance with the present invention, which is used at itsdesired clock speed in self-test or scan-test mode to detect or locatestuck-at, delay, and multiple-cycle delay faults in the design given inFIG. 7.

[0040]FIG. 9 shows a timing diagram of the full-scan design given inFIG. 7, in accordance with the present invention, where an orderedsequence of capture clocks is used to detect or locate stuck-at faultswithin each clock domain and stuck-at faults crossing clock domains inself-test mode.

[0041]FIG. 10 shows a timing diagram of the full-scan design given inFIG. 7, in accordance with the present invention, where an orderedsequence of capture clocks is used to detect or locate delay faultswithin each clock domain and stuck-at faults crossing clock domains inself-test or scan-test mode. The chain of control events is also shown.

[0042]FIG. 11 shows a timing diagram of the full-scan design given inFIG. 7, in accordance with the present invention, where a shortened yetordered sequence of capture clocks is used to detect or locate delayfaults within each clock domain and stuck-at faults crossing clockdomains in self-test or scan-test mode.

[0043]FIG. 12 shows a timing diagram of the full-scan design given inFIG. 7, in accordance with the present invention, where an orderedsequence of capture clocks is used to detect or locate stuck-at faultswithin each clock domain and delay faults crossing clock domains inself-test or scan-test mode.

[0044]FIG. 13 shows a timing diagram of the full-scan design given inFIG. 7, in accordance with the present invention, where an orderedsequence of capture clocks is used to detect or locate delay faultswithin each clock domain and delay faults crossing clock domains inself-test or scan-test mode.

[0045]FIG. 14 shows a timing diagram of the full-scan design given inFIG. 7, in accordance with the present invention, where a reorderedsequence of capture clocks is used to detect or locate delay faultswithin each clock domain and stuck-at faults crossing clock domains inself-test or scan-test mode.

[0046]FIG. 15 shows a timing diagram of the full-scan design given inFIG. 7, in accordance with the present invention, where an expanded yetordered sequence of capture clocks is used to detect or locateadditional delay faults within each clock domain and additional stuck-atfaults crossing clock domains in self-test or scan-test mode.

[0047]FIG. 16 shows a timing diagram of the full-scan design given inFIG. 7, in accordance with the present invention, where an orderedsequence of capture clocks is used to detect or locate 2-cycle delayfaults within each clock domain and stuck-at faults crossing clockdomains in self-test or scan-test mode.

[0048]FIG. 17 shows a timing diagram of the full-scan design given inFIG. 7, in accordance with the present invention, where an orderedsequence of capture clocks is used to detect or locate 2-cycle delayfaults within each clock domain and 2-cycle delay faults crossing clockdomains in self-test or scan-test mode.

[0049]FIG. 18 shows a timing diagram of the partial-scan design given inFIG. 7, in accordance with the present invention, where an orderedsequence of capture clocks is used to detect or locate stuck-at faultswithin each clock domain and stuck-at faults crossing clock domains inself-test or scan-test mode.

[0050]FIG. 19 shows a timing diagram of the partial-scan design given inFIG. 7, in accordance with the present invention, where an orderedsequence of capture clocks is used to detect or locate delay faultswithin each clock domain and stuck-at faults crossing clock domains inself-test or scan-test mode.

[0051]FIG. 20 shows a timing diagram of the partial-scan design given inFIG. 7, in accordance with the present invention, where an orderedsequence of capture clocks is used to detect or locate 2-cycle delayfaults within each clock domain and stuck-at faults crossing clockdomains in self-test or scan-test mode.

[0052]FIG. 21 shows a timing diagram of the full-scan design given inFIG. 7, in accordance with the present invention, where the captureclock CK2 during the capture cycle is chosen to diagnose faults capturedby CK2 in self-test or scan-test mode.

[0053]FIG. 22 shows a timing diagram of the full-scan design given inFIG. 7, in accordance with the present invention, where the captureclocks CK1 and CK3 during the capture cycle are chosen to diagnosefaults captured by CK1 and CK3 in self-test or scan-test mode.

[0054]FIG. 23 shows a timing diagram of the full-scan design given inFIG. 1, in accordance with the present invention, where all captureclocks during the shift cycle are skewed to reduce power consumption.

[0055]FIG. 24 shows a multiple-capture CAD system in accordance with thepresent invention, where a CAD system is used to implement themultiple-capture DFT technique on a full-scan or partial-scan design inself-test mode.

[0056]FIG. 25 shows a multiple-capture CAD system in accordance with thepresent invention, where a CAD system is used to implement themultiple-capture DFT technique on a full-scan or partial-scan design inscan-test mode.

DETAILED DESCRIPTION OF THE DRAWINGS

[0057] The following description is of presently contemplated as thebest mode of carrying out the present invention. This description is notto be taken in a limiting sense but is made merely for the purpose ofdescribing the principles of the invention. The scope of the inventionshould be determined by referring to the appended claims.

[0058]FIG. 1 shows an example full-scan or partial-scan design with amultiple-capture DFT system, of one embodiment of the invention. Thedesign 133 contains 4 clock domains, CD1 102 to CD4 105, and 4 systemclocks, CK1 111 to CK4 120. Each system clock controls one clock domain.CD1 102 and CD2 103 talk to each other via a crossing clock-domain logicblock CCD1 106; CD2 103 and CD3 104 talk to each other via a crossingclock-domain logic block CCD2 107; and CD3 104 and CD4 105 talk to eachother via a crossing clock-domain logic block CCD3 108.

[0059] The 4 clock domains, CD1 102 to CD4 105, are originally designedto run at 150 MHz, 100 MHz, 100 MHz, and 66 MHz, respectively. However,in this example, since a DFT (self-test or scan-test) technique is onlyemployed to detect or locate stuck-at faults in the design 133, allsystem clocks, CK1 111 to CK4 120, are reconfigured to operate at 10MHz. The reconfigured system clocks are called capture clocks.

[0060] During self-test or scan-test, the multiple-capture DFT system101 will take over the control of all stimuli, 109, 112, 115, and 118,all system clocks, CK1 111 to CK4 120, and all output responses, 110,113, 116, and 119.

[0061] During the shift operation, the multiple-capture DFT system 101first generates and shifts pseudorandom or predetermined stimuli through109, 112, 115, and 118 to all scan cells SC in all scan chains SCNwithin the 4 clock domains, CD1 102 to CD4 105, simultaneously. Themultiple-capture DFT system 101 shall wait until all stimuli, 109, 112,115, and 118, have been shifted into all scan cells SC. It should benoted that, during the shift operation, the capture clock can beoperated either at its rated clock speed (at-speed) or at a desiredclock speed.

[0062] After the shift operation is completed, an ordered sequence ofcapture clocks is applied to all clock domains, CD1 102 to CD4 105.During the capture operation, each capture clock can operate at itsrated clock speed (at-speed) or at a reduced speed (slow-speed), and canbe generated internally or controlled externally. In this example, allsystem clocks, CK1 111 to CK4 120, are reconfigured to operate at areduced frequency of 10 MHz.

[0063] After the capture operation is completed, the output responsescaptured at all scan cells SC are shifted out through responses 110,113, 116, and 119 to the multiple-capture DFT system 101 for compactionduring the compact operation or direct comparison during the compareoperation.

[0064] Based on FIG. 1, the timing diagrams given in FIGS. 3 to 6 areused to illustrate that, by properly ordering the sequence of captureclocks and by adjusting relative inter-clock delays, stuck-at faultswithin each clock domain and crossing clock domains can be detected orlocated in self-test or scan-test mode. Please note that different waysof ordering the sequence of capture clocks and adjusting relativeinter-clock delays will result in different faults to be detected orlocated.

[0065]FIG. 2 shows a multiple-capture DFT system with three PRPG-MISRpairs, of one embodiment of the invention, used to detect or locatestuck-at faults in the design 133 given in FIG. 1 in self-test mode.

[0066] Pseudorandom pattern generators (PRPGs), 211 to 213, are used togenerate pseudorandom patterns. Phase shifters, 214 to 216, are used tobreak the dependency between different outputs of the PRPGS. The bitstreams coming from the phase shifters become test stimuli, 109, 112,115, and 118.

[0067] Space compactors, 217 to 219, are used to reduce the number ofbit streams in test responses, 110, 113, 116, and 119. Space compactorsare optional and are only used when the overhead of a MISR becomes aconcern. The outputs of the space compactors are then compressed bymultiple input signature registers (MISRs), 220 to 222. The contents ofMISRs after all test stimuli are applied become signatures, 236 to 238.The signatures are then be compared by comparators, 223 to 225, withcorresponding expected values. The error indicator 226 is used tocombine the individual pass/fail signals, 242 to 244, a global pass/failsignal 245. Alternatively, the signatures in MISRs 220 to 222 can beshifted to the outside of the design for comparison through a singlescan chain composed of elements 223, 239, 224, 240, 225, and 241.

[0068] The central self-test controller 202 controls the whole testprocess by manipulating individual scan enable signals, 204 to 207, andby reconfiguring capture clocks, CK1 111 to CK4 120. Especially, thescan enable signals, 204 to 207, can be controlled by one global scanenable signal GSE 201, which can be a slow signal in that it does nothave to settle down in half of the cycle of any clock applied to anyclock domain. Some additional control signals 203 are needed to conductother control tasks.

[0069] The clock domains 103 and 104, which are operated at the samefrequency, share the same pair of PRPG 212 and MISR 221. It should benoted that the skew between the clocks CK2 114 and CK3 117 should beproperly managed to prevent any timing violations during the shiftoperation and any races during the capture operation.

[0070] All storage elements in PRPGs, 211 to 213, and MISRs, 220 to 222,can be connected into a scan chain from which predetermined patterns canbe shifted in for reseeding and computed signatures can be shifted outfor analysis. This configuration helps in increasing fault coverage andin facilitating fault diagnosis.

[0071]FIG. 3 shows a timing diagram of a full-scan design given in FIG.1, of one embodiment of the invention for detecting or locating stuck-atfaults within each clock domain and stuck-at faults crossing clockdomains with an ordered sequence of capture clocks in self-test mode.The timing diagram 300 shows the sequence of waveforms of the 4 captureclocks, CK1 111 to CK4 120, operating at the same frequency.

[0072] During each shift cycle 310, a series of pulses of 10 MHz areapplied through capture clocks, CK1 111 to CK4 120, to shift stimuli toall scan cells within all clock domains, CD1 102 to CD4 105.

[0073] During each capture cycle 311, 4 sets of capture clock pulses areapplied in the following order: First, one capture pulse is applied toCK1 111 to detect or locate stuck-at faults within the clock domain CD1102. Second, one capture pulse is applied to CK2 114 to detect or locatestuck-at faults within the clock domain CD2 103. Third, one capturepulse is applied to CK3 117 to detect or locate stuck-at faults withinthe clock domain CD3 104. Fourth, one capture pulse is applied to CK4120 to detect or locate stuck-at faults within the clock domain CD4 105.

[0074] In addition, the stuck-at faults which can be reached from lines121, 125, and 129 in the crossing clock-domain logic blocks CCD1 106 toCCD3 108, respectively, are also detected or located simultaneously ifthe following condition is satisfied: The relative clock delay 307between the rising edge of the capture pulse of CK1 111 and the risingedge of the capture pulse of CK2 114 must be adjusted so that no racesor timing violations would occur while the output responses 123 arecaptured through the crossing clock-domain logic block CCD1 106.

[0075] The same principle applies to the relative clock delay 308between CK2 114 and CK3 117, and the relative clock delay 309 betweenCK3 117 and CK4 120 for capturing output responses, 127 and 131, throughCCD2 107 and CCD3 108, respectively.

[0076] It should be noticed that, generally, during each shift cycle,any capture clock is allowed to operate at its desired or a reducedclock speed. In addition, it is not necessary that all capture clocksmust operate at the same clock speed. Furthermore, to reduce peak powerconsumption during the shift cycle, all capture clocks can be skewed sothat at any given time only scan cells within one clock domain canchange states. One global scan enable signal GSE 201, operated at areduced clock speed, can also be used, when requested, to switch thetest operation from the shift cycle to the capture cycle, and viceversa.

[0077] The daisy-chain clock-triggering technique is used to generateand order the sequence of capture clocks one after the other in thefollowing way: The rising edge of the last pulse in the shift cycletriggers the event 301 of applying 0 to the global scan enable GSE 201,switching the test operation from the shift cycle to the capture cycle.The falling edge of GSE 201 triggers the event 302 of applying onecapture pulse to CK1 111. Similarly, the rising edge of the capturepulse of CK1 111 triggers the event 303 of applying one capture pulse toCK2 114, the rising edge of the capture pulse of CK2 114 triggers theevent 304 of applying one capture pulse to CK3 117, and the rising edgeof the capture pulse of CK3 117 triggers the event 305 of applying onecapture pulse to CK4 120. Finally, the rising edge of the capture pulseof CK4 120 triggers the event 306 of applying 1 to the global scanenable GSE 201, switching the test operation from the capture cycle tothe shift cycle. This daisy-chain clock-triggering technique is alsoused to order the sequence of capture clocks in FIGS. 4 to 6.

[0078]FIG. 4 shows a timing diagram of a full-scan design given in FIG.1, of one embodiment of the invention for detecting or locating stuck-atfaults within each clock domain and stuck-at faults crossing clockdomains with a shortened yet ordered sequence of capture clocks inself-test mode. The timing diagram 400 shows the sequence of waveformsof the 4 capture clocks, CK1 111 to CK4 120, operating at the samefrequency.

[0079] During each shift cycle 402, a series of clock pulses of 10 MHzare applied through capture clocks, CK1 111 to CK4 120, to shift stimulito all scan cells within all clock domains, CD1 102 to CD4 105.

[0080] During each capture cycle 403, two sets of capture clock pulsesare applied in the following order: First, one capture pulse is appliedto CK1 111 and CK3 117 simultaneously to detect or locate stuck-atfaults within the clock domain CD1 102 and CD3 104, respectively.Second, one capture pulse is applied to CK2 114 and CK4 120simultaneously to detect or locate stuck-at faults within the clockdomain CD2 103 and CD4 105, respectively.

[0081] In addition, the stuck-at faults which can be reached from lines121, 128, and 129 in the crossing clock-domain logic blocks CCD1 106 toCCD3 108, respectively, are also detected or located simultaneously ifthe following condition is satisfied: The relative clock delay 401between the rising edge of the capture pulse for CK1 111 and CK3 117 andthe rising edge of the capture pulse for CK2 114 and CK4 120, must beadjusted so that no races or timing violations would occur while theoutput responses, 123, 126, and 131, are captured through the crossingclock-domain logic blocks CCD1 106 to CCD3 108.

[0082]FIG. 5 shows a timing diagram of a full-scan design in FIG. 1 ofone embodiment of the invention for detecting or locating otherstuck-type faults within each clock domain and other stuck-type faultscrossing clock domains with an expanded yet ordered sequence of captureclocks in self-test or scan-test mode. The timing diagram 500 shows thesequence of waveforms of the 4 capture clocks, CK1 111 to CK4 120,operating at the same frequency.

[0083] During each shift cycle 503, a series of clock pulses of 10 MHzare applied through capture clocks, CK1 111 to CK4 120, to shift stimulito all scan cells within all clock domains, CD1 102 to CD4 105.

[0084] During each capture cycle 504, two sets of capture clock pulsesare applied in the following order: First, two capture pulses areapplied to CK1 111 and CK3 117, simultaneously. Second, one capturepulse is applied to CK2 114 and CK4 120, simultaneously. Stuck-at faultsin all crossing clock-domain combinations, from 121 to 123, from 124 to122, from 125 to 127, from 128 to 126, from 129 to 131, from 132 to 130,can be detected or located if the following condition is satisfied: Therelative clock delay 501 between the rising edge of the first capturepulse of CK1 111 and CK3 117 and the rising edge of the capture pulse ofCK2 114 and CK4 120 must be adjusted so that no races or timingviolations would occur while the output responses 123, 126, and 131 arecaptured through the crossing clock-domain logic block CCD1 106 to CCD3108, respectively. The relative clock delay 502 between the rising edgeof the capture pulse of CK2 114 and CK4 120 and the second capture pulseof CK1 111 and CK3 117 must be adjusted so that no races or timingviolations would occur while the output responses 122, 127, and 130 arecaptured through the crossing clock-domain logic block CCD1 106 to CCD3108, respectively.

[0085]FIG. 6 shows a timing diagram of a feed-forward partial-scandesign given in FIG. 1, of one embodiment of the invention for detectingor locating stuck-at faults within each clock domain and stuck-at faultscrossing clock domains with a shortened yet ordered sequence of captureclocks in self-test or scan-test mode. It is assumed that the clockdomains CD1 102 to CD4 105 contain a number of un-scanned storage cellsthat form a sequential depth of no more than 2. The timing diagram 600shows the sequence of waveforms of the 4 capture clocks, CK1 111 to CK4120, operating at the same frequency.

[0086] During each shift cycle 606, a series of clock pulses of 10 MHzare applied through capture clocks, CK1 111 to CK4 120, to shift stimulito all scan cells within all clock domains, CD1 102 to CD4 105.

[0087] During each capture cycle 607, two sets of capture clock pulsesare applied in the following order: First, three pulses of 10 MHz, twobeing functional pulses and one being a capture pulse, are applied toCK1 111 and CK3 117 simultaneously to detect or locate stuck-at faultswithin the clock domain CD1 102 and CD3 104, respectively. Second, threepulses of 10 MHz, two being functional pulses and one being a capturepulse, are applied to CK2 114 and CK4 120 simultaneously to detect orlocate stuck-at faults within the clock domain CD2 103 and CD4 105,respectively.

[0088] In addition, the stuck-at faults which can be reached from lines121, 128, and 129 in the crossing clock-domain logic blocks CCD1 106 toCCD3 108, respectively, are also detected or located simultaneously ifthe following condition is satisfied: The relative clock delay 603between the rising edge of the capture pulse for CK1 111 and CK3 117 andthe rising edge of the capture pulse for CK2 114 and CK4 120 must beadjusted so that no races or timing violations would occur while theoutput responses, 123, 126, and 131, are captured through the crossingclock-domain logic blocks CCD1 106 to CCD3 108.

[0089]FIG. 7 shows an example full-scan or partial-scan design with amultiple-capture DFT system, of one embodiment of the invention. Thedesign 733 is the same as the design 133 given in FIG. 1. Same as inFIG. 1, the 4 clock domains, CD1 702 to CD4 705, are originally designedto run at 150 MHz, 100 MHz, 100 MHz, and 66 MHz, respectively. The onlydifference from FIG. 1 is that these clock frequencies will be useddirectly without alternation in order to implement at-speed self-test orscan-test for stuck-at, delay, and multiple-cycle delay faults withineach clock domain and crossing clock domains.

[0090] Based on FIG. 7, the timing diagrams given in FIGS. 9 to 20 areused to illustrate that, by properly ordering the sequence of capturepulses and by adjusting relative inter-clock delays, the at-speeddetection or location of stuck-at, delay, and multiple-cycle delayfaults within each clock domain and crossing clock domains can beachieved in self-test or scan-test mode. Please note that different waysof ordering the sequence of capture pulses and adjusting relativeinter-clock delays will result in different faults to be detected orlocated.

[0091]FIG. 8 shows a multiple-capture DFT system with three PRPG-MISRpairs, of one embodiment of the invention, used in self-test orscan-test mode to detect or locate stuck-at, delay, and multiple-cycledelay faults in the design given in FIG. 7. The composition andoperation of the multiple-capture DFT system is basically the same asthe one given in FIG. 2. There are two major differences: One is that,in this example, the original clock frequencies, 150 MHz, 100 MHz, 100MHz, and 66 MHz, are used directly without alternation in order toimplement at-speed self-test or scan-test. The other is that more careneeds to be taken in the physical design of scan chains, etc., in thisexample.

[0092] The clock domains 703 and 704, which are operated at the samefrequency, share the same pair of PRPG 812 and MISR 821. It should benoted that the skew between the clocks CK2 714 and CK3 717 should beproperly managed to prevent any timing violations during the shiftoperation and any races during the capture operation.

[0093] All storage elements in PRPGs, 811 to 813, and MISRs, 820 to 822,can be connected into a scan chain from which predetermined patterns canbe shifted in for reseeding and computed signatures can be shifted outfor analysis. This configuration helps in increasing fault coverage andin facilitating fault diagnosis.

[0094]FIG. 9 shows a timing diagram of a full-scan design given in FIG.7, of one embodiment of the invention for detecting or locating stuck-atfaults within each clock domain and stuck-at faults crossing clockdomains with an ordered sequence of capture clocks in self-test mode.The timing diagram 900 shows the sequence of waveforms of the 4 captureclocks, CK1 711 to CK4 720, operating at different frequencies. Thistiming diagram is basically the same as the one given in FIG. 3 exceptthe capture clocks, CK1 711 to CK4 720, run at 150 MHz, 100 MHz, 100MHz, and 66 MHz, respectively, in both shift and capture cycles, insteadof 10 MHz as in FIG. 3.

[0095]FIG. 10 shows a timing diagram of a full-scan design given in FIG.7, of one embodiment of the invention for detecting or locating delayfaults within each clock domain and stuck-at faults crossing clockdomains with an ordered sequence of capture clocks in self-test orscan-test mode. The timing diagram 1000 shows the sequence of waveformsof the 4 capture clocks, CK1 711 to CK4 720, operating at differentfrequencies.

[0096] During each shift cycle 1014, a series of clock pulses ofdifferent frequencies, 150 MHz, 100 MHz, 100 MHz, and 66 MHz, areapplied through capture clocks, CK1 711 to CK4 720, to shift stimuli toall scan cells within all clock domains, CD1 702 to CD4 705.

[0097] During each capture cycle 1015, 4 sets of capture clock pulsesare applied in the following order: First, two capture pulses of 150 MHzare applied to CK1 711 to detect or locate delay faults within the clockdomain CD1 702. Second, two capture pulses of 100 MHz are applied to CK2714 to detect or locate delay faults within the clock domain CD2 703.Third, two capture pulses of 100 MHz are applied to CK3 717 to detect orlocate delay faults within the clock domain CD3 704. Fourth, two capturepulses of 66 MHz are applied to CK4 720 to detect or locate delay faultswithin the clock domain CD4 705.

[0098] In addition, the stuck-at faults which can be reached from lines721, 725, and 729 in the crossing clock-domain logic blocks CCD1 706 toCCD3 708, respectively, are also detected or located simultaneously ifthe following condition is satisfied: The relative clock delay 1008between the rising edge of the second capture pulse of CK1 711 and therising edge of the first capture pulse of CK2 714 must be adjusted sothat no races or timing violations would occur while the outputresponses 723 are captured through the crossing clock-domain logic blockCCD1 706.

[0099] The same principle applies to the relative clock delay 1010between CK2 714 and CK3 717, and the relative clock delay 1012 betweenCK3 717 and CK4 720 for capturing the output responses, 727 and 731,through CCD2 707 and CCD3 708, respectively.

[0100] The daisy-chain clock-triggering technique is used to generateand order the sequence of capture clocks one after the other in thefollowing way: The rising edge of the last pulse in the shift cycletriggers the event 1001 of applying 0 to the global scan enable GSE 801,switching the test operation from the shift cycle to the capture cycle.The falling edge of GSE 801 triggers the event 1002 of applying twocapture pulses to CK1 711. Similarly, the rising edge of the secondcapture pulse of CK1 711 triggers the event 1003 of applying two capturepulses to CK2 714, the rising edge of the second capture pulse of CK2714 triggers the event 1004 of applying two capture pulses to CK3 717,and the rising edge of the second capture pulse of CK3 717 triggers theevent 1005 of applying two capture pulses to CK4 720. Finally, therising edge of the second capture pulse of CK4 720 triggers the event1006 of applying 1 to the global scan enable GSE 801, switching the testoperation from the capture cycle to the shift cycle. This daisy-chainclock-triggering technique is also used to order the sequence of captureclocks in FIG. 9 and FIGS. 11 to 20.

[0101]FIG. 11 shows a timing diagram of a full-scan design given in FIG.7, of one embodiment of the invention for detecting or locating delayfaults within each clock domain and stuck-at faults crossing clockdomains with a shortened yet ordered sequence of capture clocks inself-test or scan-test mode. The timing diagram 1100 shows the sequenceof waveforms of the 4 capture clocks, CK1 711 to CK4 720, operating atdifferent frequencies.

[0102] During each shift cycle 1108, a series of clock pulses ofdifferent frequencies, 150 MHz, 100 MHz, 100 MHz, and 66 MHz, areapplied through capture clocks, CK1 711 to CK4 720, to shift stimuli toall scan cells within all clock domains, CD1 702 to CD4 705.

[0103] During each capture cycle 1109, 4 sets of capture clock pulsesare applied in the following order: First, two capture pulses offrequency 150 MHz are applied to CK1 711 and two clock pulses offrequency 100 MHz are applied to CK3 717, simultaneously, to detect orlocate delay faults within the clock domain CD1 702 and CD3 704,respectively. Second, two capture pulses of frequency 100 MHz areapplied to CK2 714 and two capture pulses of frequency 66 MHz areapplied to CK4 720, simultaneously, to detect or locate delay faultswithin the clock domain CD2 703 and CD4 705, respectively.

[0104] In addition, the stuck-at faults which can be reached from lines721, 728, and 729 in the crossing clock-domain logic blocks CCD1 706 toCCD3 708, respectively, are also detected or located simultaneously ifthe following condition is satisfied: The relative clock delay 1102between the rising edge of the second capture pulse of CK1 711 and therising edge of the first capture pulse of CK2 714 must be adjusted sothat no races or timing violations would occur while the outputresponses 723 are captured through the crossing clock-domain logic blockCCD1 706.

[0105] The same principle applies to the relative clock delay 1104between CK3 717 and CK2 714, and the relative clock delay 1106 betweenCK3 717 and CK4 720 for capturing the output responses, 726 and 731,through CCD2 707 and CCD3 708, respectively.

[0106]FIG. 12 shows a timing diagram of a full-scan design given in FIG.7, of one embodiment of the invention for detecting or locating stuck-atfaults within each clock domain and delay faults crossing clock domainswith an ordered sequence of capture clocks in self-test or scan-testmode. The timing diagram 1200 shows the sequence of waveforms of the 4capture clocks, CK1 711 to CK4 720, operating at different frequencies.

[0107] During each shift cycle 1204, a series of clock pulses ofdifferent frequencies, 150 MHz, 100 MHz, 100 MHz, and 66 MHz, areapplied through capture clocks, CK1 711 to CK4 720, to shift stimuli toall scan cells within all clock domains, CD1 702 to CD4 705.

[0108] During each capture cycle 1205, 4 sets of capture clock pulsesare applied in the following order: First, one capture pulse of 150 MHzis applied to CK1 711 to detect or locate stuck-at faults within theclock domain CD1 702. Second, one capture pulse of 100 MHz is applied toCK2 714 to detect or locate stuck-at faults within the clock domain CD2703. Third, one capture pulse of 100 MHz is applied to CK3 717 to detector locate stuck-at faults within the clock domain CD3 704. Fourth, onecapture pulse of 66 MHz is applied to CK4 720 to detect or locatestuck-at faults within the clock domain CD4 705.

[0109] In addition, the delay faults which can be reached from lines721, 725, and 729 in the crossing clock-domain logic blocks CCD1 706 toCCD3 708, respectively, are also detected or located simultaneously ifthe following condition is satisfied: The relative clock delays 1201between the rising edge of the capture pulse of CK1 711 and the risingedge of the capture pulse of CK2 714 must be adjusted to meet theat-speed timing requirements for paths from 721 to 723. Similarly, therelative clock delay 1202 between CK2 714 and CK3 717, and the relativeclock delay 1203 between CK3 717 and CK4 720, must be adjusted to meetthe at-speed timing requirements for paths from 725 to 727, and pathsfrom 729 to 731, respectively.

[0110]FIG. 13 shows a timing diagram of a full-scan design given in FIG.7, of one embodiment of the invention for detecting or locating delayfaults within each clock domain and delay faults crossing clock domainswith an ordered sequence of capture clocks in self-test or scan-testmode. The timing diagram 1300 shows the sequence of waveforms of the 4capture clocks, CK1 711 to CK4 720, operating at different frequencies.

[0111] During each shift cycle 1308, a series of clock pulses ofdifferent frequencies, 150 MHz, 100 MHz, 100 MHz, and 66 MHz, areapplied through capture clocks, CK1 711 to CK4 720, to shift stimuli toall scan cells within all clock domains, CD1 702 to CD4 705.

[0112] During each capture cycle 1309, 4 sets of capture clock pulsesare applied in the following order: First, two capture pulses of 150 MHzare applied to CK1 711 to detect or locate delay faults within the clockdomain CD1 702. Second, two capture pulses of 100 MHz are applied to CK2714 to detect or locate delay faults within the clock domain CD2 703.Third, two capture pulses of 100 MHz are applied to CK3 717 to detect orlocate delay faults within the clock domain CD3 704. Fourth, two capturepulses of 66 MHz are applied to CK4 720 to detect or locate delay faultswithin the clock domain CD4 705.

[0113] In addition, the delay faults which can be reached from lines721, 725, and 729 in the crossing clock-domain logic blocks CCD1 706 toCCD3 708, respectively, are also detected or located simultaneously ifthe following condition is satisfied: The relative clock delay 1302between the rising edge of the second capture pulse of CK1 711 and therising edge of the first capture pulse of CK2 714 must be adjusted tomeet the at-speed timing requirements for paths from 721 to 723.Similarly, the relative clock delay 1304 between CK2 714 and CK3 717,and the relative clock delay 1306 between CK3 717 and CK4 720, must beadjusted to meet the at-speed timing requirements for paths from 725 to727, and paths from 729 and 731, respectively.

[0114]FIG. 14 shows a timing diagram of a full-scan design given in FIG.7, of one embodiment of the invention for detecting or locating delayfaults within each clock domain and stuck-at faults crossing clockdomains with a reordered sequence of capture clocks in self-test orscan-test mode. The timing diagram 1400 shows the sequence of waveformsof the 4 capture clocks, CK1 711 to CK4 720, operating at differentfrequencies.

[0115] During each shift cycle 1408, a series of clock pulses ofdifferent frequencies, 150 MHz, 100 MHz, 100 MHz, and 66 MHz, areapplied through capture clocks, CK1 711 to CK4 720, to shift stimuli toall scan cells within all clock domains, CD1 702 to CD4 705.

[0116] During each capture cycle 1409, 4 sets of capture clock pulsesare applied in the following order: First, two capture pulses of 66 MHzare applied to CK4 720 to detect or locate delay faults within the clockdomain CD4 705. Second, two capture pulses of 100 MHz are applied to CK3717 to detect or locate delay faults within the clock domain CD3 704.Third, two capture pulses of 100 MHz are applied to CK2 714 to detect orlocate delay faults within the clock domain CD2 703. Fourth, two capturepulses of 150 MHz are applied to CK1 711 to detect or locate delayfaults within the clock domain CD1 702.

[0117] In addition, the stuck-at faults which can be reached from lines724, 728, and 732 in the crossing clock-domain logic blocks CCD1 706 toCCD3 708, respectively, are also detected or located simultaneously ifthe following condition is satisfied: The relative clock delay 1402between the rising edge of the second capture pulse of CK4 720 and therising edge of the first capture pulse of CK3 717 must be adjusted sothat no races or timing violations would occur while the outputresponses 730 are captured through the crossing clock-domain logic blockCCD3 708.

[0118] The same principle applies to the relative clock delay 1404between CK3 717 and CK2 714, and the relative clock delay 1406 betweenCK2 714 and CK1 711 for capturing output responses, 726 and 722, throughCCD2 707 and CCD1 706, respectively.

[0119]FIG. 15 shows a timing diagram of a full-scan design given in FIG.7, of one embodiment of the invention for detecting or locatingadditional delay faults within each clock domain and additional stuck-atfaults crossing clock domains with an expanded yet ordered sequence ofcapture clocks in self-test or scan-test mode. The timing diagram 1500shows the sequence of waveforms of the 4 capture clocks, CK1 711 to CK4720, operating at different frequencies.

[0120] During each shift cycle 1514, a series of clock pulses ofdifferent frequencies, 150 MHz, 100 MHz, 100 MHz, and 66 MHz, areapplied through capture clocks, CK1 711 to CK4 720, to shift stimuli toall scan cells within all clock domains, CD1 702 to CD4 705.

[0121] During each capture cycle 1515, seven sets of double-capturepulses are applied in the following order: First, two capture pulses of150 MHz are applied to CK1 711. Second, two capture pulses of 100 MHzare applied to CK2 714. Third, two capture pulses of 100 MHz are appliedto CK3 717. Fourth, two capture pulses of 66 MHz are applied to CK4 720.Fifth, two capture pulses of 100 MHz are applied to CK3 717. Sixth, twocapture pulses of 100 MHz are applied to CK2 714. Seventh, two capturepulses of 150 MHz are applied to CK1 711.

[0122] For the capture clock CK1 711, the second pulse and the thirdpulse are used to launch the transition needed for detecting or locatingdelay faults within the clock domain CD1 702. Since the transition isgenerated by two close-to-functional patterns, the risk of activating afalse path is lower. In addition, additional delay faults within theclock domain CD1 702 can be detected or located by the transition. Thesame results also apply to the clock domains CD2 703 and CD3 704.

[0123] In addition, the stuck-at faults which can be reached from lines724, 728, and 732 in the crossing clock-domain logic blocks CCD1 706 toCCD3 708, respectively, are also detected or located simultaneously ifthe following condition is satisfied: The relative clock delay 1508between the rising edge of the second capture pulse of CK4 720 and therising edge of the first capture pulse of CK3 717 must be adjusted sothat no races or timing violations would occur while the outputresponses 730 are captured through the crossing clock-domain logic blockCCD3 708.

[0124] The same principle applies to the relative clock delay 1510between CK3 717 and CK2 714, and the relative clock delay 1512 betweenCK2 714 and CK1 711 for capturing output responses, 726 and 722, throughCCD2 707 and CCD1 706, respectively.

[0125]FIG. 16 shows a timing diagram of a full-scan design given in FIG.7, of one embodiment of the invention for detecting or locating 2-cycledelay faults within each clock domain and stuck-at faults crossing clockdomains with an ordered sequence of capture clocks in self-test orscan-test mode. It is assumed that some paths in the clock domains, CD1702 to CD4 705, need two cycles for signals to pass through. The timingdiagram 1600 shows the sequence of waveforms of the 4 capture clocks,CK1 711 to CK4 720, operating at different frequencies.

[0126] During each shift cycle 1608, a series of clock pulses ofdifferent frequencies, 150 MHz, 100 MHz, 100 MHz, and 66 MHz, areapplied through capture clocks, CK1 711 to CK4 720, to shift stimuli toall scan cells within all clock domains, CD1 702 to CD4 705.

[0127] During each capture cycle 1609, 4 sets of capture clock pulsesare applied in the following order: First, two capture pulses of 75 MHz(half of 150 MHz) are applied to CK1 711 to detect or locate 2-cycledelay faults within the clock domain CD1 702. Second, two capture pulsesof 50 MHz (half of 100 MHz) are applied to CK2 714 to detect or locate2-cycle delay faults within the clock domain CD2 703. Third, two capturepulses of 50 MHz (half of 100 MHz) are applied to CK3 717 to detect orlocate 2-cycle delay faults within the clock domain CD3 704. Fourth, twocapture pulses of 33 MHz (half of 66 MHz) are applied to CK4 720 todetect or locate 2-cycle delay faults within the clock domain CD4 705.

[0128] In addition, the stuck-at faults which can be reached from lines721, 725, and 729 in the crossing clock-domain logic blocks CCD1 706 toCCD3 708, respectively, are also detected or located simultaneously ifthe following condition is satisfied: The relative clock delay 1602between the rising edge of the second capture pulse of CK1 711 and therising edge of the first capture pulse of CK2 714 must be adjusted sothat no races or timing violations would occur while the outputresponses 723 are captured through the crossing clock-domain logic blockCCD1 706.

[0129] The same principle applies to the relative clock delay 1604between CK2 714 and CK3 717, and the relative clock delay 1606 betweenCK3 717 and CK4 720 for capturing output responses, 727 and 731, throughCCD2 707 and CCD3 708, respectively.

[0130]FIG. 17 shows a timing diagram of a full-scan design given in FIG.7, of one embodiment of the invention for detecting or locating 2-cycledelay faults within each clock domain and 2-cycle delay faults crossingclock domains with an ordered sequence of capture clocks in self-test orscan-test mode. It is assumed that some paths in the clock domains, CD1702 to CD4 705, and the crossing clock-domain logic blocks, CCD1 706 toCCD3 708, need two cycles for signals to pass through. The timingdiagram 1700 shows the sequence of waveforms of the 4 capture clocks,CK1 711 to CK4 720, operating at different frequencies.

[0131] During each shift cycle 1708, a series of clock pulses ofdifferent frequencies, 150 MHz, 100 MHz, 100 MHz, and 66 MHz, areapplied through capture clocks, CK1 711 to CK4 720, to shift stimuli toall scan cells within all clock domains, CD1 702 to CD4 705.

[0132] During each capture cycle 1709, 4 sets of capture clock pulsesare applied in the following order: First, two capture pulses of 75 MHz(half of 150 MHz) are applied to CK1 711 to detect or locate 2-cycledelay faults within the clock domain CD1 702. Second, two capture pulsesof 50 MHz (half of 100 MHz) are applied to CK2 714 to detect or locate2-cycle delay faults within the clock domain CD2 703. Third, two capturepulses of 50 MHz (half of 100 MHz) are applied to CK3 717 to detect orlocate 2-cycle delay faults within the clock domain CD3 704. Fourth, twocapture pulses of 33 MHz (half of 66 MHz) are applied to CK4 720 todetect or locate 2-cycle delay faults within the clock domain CD4 705.

[0133] In addition, the 2-cycle delay faults which can be reached fromlines 721, 725, and 729 in the crossing clock-domain logic blocks CCD1706 to CCD3 708, respectively, are also detected or locatedsimultaneously if the following condition is satisfied: The relativeclock delay 1702 between the rising edge of the second capture pulse ofCK1 711 and the rising edge of the first capture pulse of CK2 714 mustbe adjusted to meet the 2-cycle timing requirements for paths from 721to 723. Similarly, the relative clock delay 1704 between CK2 714 and CK3717, and the relative clock delay 1706 between CK3 717 and CK4 720, mustbe adjusted to meet the 2-cycle timing requirements for paths from 725to 727, and paths from 729 and 731, respectively.

[0134]FIG. 18 shows a timing diagram of a feed-forward partial-scandesign given in FIG. 7, of one embodiment of the invention for detectingor locating stuck-at faults within each clock domain and stuck-at faultscrossing clock domains with an ordered sequence of capture clocks inself-test or scan-test mode. It is assumed that the clock domains CD1702 to CD4 705 contain a number of un-scanned storage cells that form asequential depth of no more than 2. The timing diagram 1800 shows thesequence of waveforms of the 4 capture clocks, CK1 711 to CK4 720,operating at different frequencies.

[0135] During each shift cycle 1812, a series of clock pulses ofdifferent frequencies, 150 MHz, 100 MHz, 100 MHz, and 66 MHz, areapplied through capture clocks, CK1 711 to CK4 720, to shift stimuli toall scan cells within all clock domains, CD1 702 to CD4 705.

[0136] During each capture cycle 1813, 4 sets of capture clock pulsesare applied in the following order: First, three pulses of 150 MHz, twobeing functional pulses and one being a capture pulse, are applied toCK1 711 to detect or locate stuck-at faults within the clock domain CD1702. Second, three pulses of 100 MHz, two being functional pulses andone being a capture pulse, are applied to CK2 714 to detect or locatestuck-at faults within the clock domain CD2 703. Third, three pulses of100 MHz, two being functional pulses and one being a capture pulse, areapplied to CK3 717 to detect or locate stuck-at faults within the clockdomain CD3 704. Fourth, three pulses of frequency 66 MHz, two beingfunctional pulses and one being a capture pulse, are applied to CK4 717to detect or locate stuck-at faults within the clock domain CD4 705.

[0137] In addition, the stuck-at faults which can be reached from lines721, 725, and 729 in the crossing clock-domain logic blocks CCD1 706 toCCD3 708, respectively, are also detected or located simultaneously ifthe following condition is satisfied: The relative clock delay 1803between the rising edge of the second capture pulse of CK1 711 and therising edge of the first capture pulse of CK2 714 must be adjusted sothat no races or timing violations would occur while the outputresponses 723 are captured through the crossing clock-domain logic blockCCD1 706.

[0138] The same principle applies to the relative clock delay 1806between CK2 714 and CK3 717, and the relative clock delay 1809 betweenCK3 717 and CK4 720 for capturing output responses, 727 and 731, throughCCD2 707 and CCD3 708, respectively.

[0139]FIG. 19 shows a timing diagram of a feed-forward partial-scandesign given in FIG. 7, of one embodiment of the invention for detectingor locating delay faults within each clock domain and stuck-at faultscrossing clock domains with an ordered sequence of capture clocks inself-test or scan-test mode. It is assumed that the clock domains CD1702 to CD4 705 contain a number of un-scanned storage cells that form asequential depth of no more than 2. The timing diagram 1900 shows thesequence of waveforms of the 4 capture clocks, CK1 711 to CK4 720,operating at different frequencies.

[0140] During each shift cycle 1916, a series of clock pulses ofdifferent frequencies, 150 MHz, 100 MHz, 100 MHz, and 66 MHz, areapplied through capture clocks, CK1 711 to CK4 720, to shift stimuli toall scan cells within all clock domains, CD1 702 to CD4 705.

[0141] During each capture cycle 1917, 4 sets of capture clock pulsesare applied in the following order: First, 4 pulses of 150MHZ, two beingfunctional pulses and two being capture pulses, are applied to CK1 711to detect or locate delay faults within the clock domain CD1 702.Second, 4 pulses of 100 MHz, two being functional pulses and two beingcapture pulses, are applied to CK2 714 to detect or locate delay faultswithin the clock domain CD2 703. Third, 4 pulses of 100 MHz, two beingfunctional pulses and two being capture pulses, are applied to CK3 717to detect or locate delay faults within the clock domain CD3 704.Fourth, 4 pulses of 66 MHz, two being functional pulses and two beingcapture pulses, are applied to CK4 720 to detect or locate delay faultswithin the clock domain CD4 705.

[0142] In addition, the stuck-at faults which can be reached from lines721, 725, and 729 in the crossing clock-domain logic blocks CCD1 706 toCCD3 708, respectively, are also detected or located simultaneously ifthe following condition is satisfied: The relative clock delay 1904between the rising edge of the second capture pulse of CK1 711 and therising edge of the first capture pulse of CK2 714 must be adjusted sothat no races or timing violations would occur while the outputresponses 723 are captured through the crossing clock-domain logic blockCCD1 706.

[0143] The same principle applies to the relative clock delay 1908between CK2 714 and CK3 717, and the relative clock delay 1912 betweenCK3 717 and CK4 720 for capturing output responses, 727 and 731, throughCCD2 707 and CCD3 708, respectively.

[0144]FIG. 20 shows a timing diagram of a feed-forward partial-scandesign given in FIG. 7, of one embodiment of the invention for detectingor locating 2-cycle delay faults within each clock domain and stuck-atfaults crossing clock domains with an ordered sequence of capture clocksin self-test or scan-test mode. It is assumed that the clock domains CD1702 to CD4 705 contain a number of un-scanned storage cells that form asequential depth of no more than 2. Also, it is assumed that some pathsin the clock domains, CD1 702 to CD4 705, need two cycles for signals topass through. The timing diagram 2000 shows the sequence of waveforms ofthe 4 capture clocks, CK1 711 to CK4 720, operating at differentfrequencies.

[0145] During each shift cycle 2016, a series of clock pulses ofdifferent frequencies, 150 MHz, 100 MHz, 100 MHz, and 66 MHz, areapplied through capture clocks, CK1 711 to CK4 720, to shift stimuli toall scan cells within all clock domains, CD1 702 to CD4 705.

[0146] During each capture cycle 2017, 4 sets of capture clock pulsesare applied in the following order: First, 4 pulses, two beingfunctional pulses of 150 MHz and two being capture pulses of 75 MHz(half of 150 MHz), are applied to CK1 711 to detect or locate 2-cycledelay faults within the clock domain CD1 702. Second, 4 pulses, twobeing functional pulses of 100 MHz and two being capture pulses of 50MHz (half of 100 MHz), are applied to CK2 714 to detect or locate2-cycle delay faults within the clock domain CD2 703. Third, 4 pulses,two being functional pulses of 100 MHz and two being capture pulses of50 MHz (half of 100 MHz), are applied to CK3 717 to detect or locate2-cycle delay faults within the clock domain CD3 704. Fourth, 4 pulses,2 being functional pulses of 66 MHz and 2 being capture pulses of 33 MHz(half of 66 MHz), are applied to CK4 720 to detect or locate 2-cycledelay faults within the clock domain CD4 705.

[0147] In addition, the stuck-at faults which can be reached from lines721, 725, and 729 in the crossing clock-domain logic blocks CCD1 706 toCCD3 708, respectively, are also detected or located simultaneously ifthe following condition is satisfied: The relative clock delay 2004between the rising edge of the second capture pulse of CK1 711 and therising edge of the first capture pulse of CK2 714 must be adjusted sothat no races or timing violations would occur while the outputresponses 723 are captured through the crossing clock-domain logic blockCCD1 706.

[0148] The same principle applies to the relative clock delay 2008between CK2 714 and CK3 717, and the relative clock delay 2012 betweenCK3 717 and CK4 720 for capturing output responses, 727 and 731, throughCCD2 707 and CCD3 708, respectively.

[0149]FIG. 21 shows a timing diagram of the full-scan design given inFIG. 7, in accordance with the present invention, where the captureclock CK2 during the capture cycle is chosen to diagnose faults capturedby CK2 in self-test or scan-test mode.

[0150] Fault diagnosis is the procedure by which a fault is located. Inorder to achieve this goal, it is often necessary to use an approachwhere a test pattern detects only portion of faults while guaranteeingno other faults are detected. If the test pattern does produce aresponse that matches the observed response, it can then be declaredthat the portion must contain at least one actual fault. Then the sameapproach to the portion of the faults to further localize the actualfaults.

[0151] The timing diagram 2100 shows a way to facilitate this approach.In the capture cycle 2107, two capture pulses of 100 MHz are onlyapplied to the capture clock CK2 714 while the other three captureclocks are held inactive. As a result, for delay faults, only those inthe clock domain CD2 703 are detected. In addition, for stuck-at faults,only those in the crossing clock-domain logic blocks CCD1 706 and CCD2707 and the clock domain CD2 703 are detected. Obviously, this clocktiming helps in fault diagnosis.

[0152]FIG. 22 shows a timing diagram of the full-scan design given inFIG. 7, in accordance with the present invention, where the captureclocks CK1 and CK3 during the capture cycle are chosen to diagnosefaults captured by CK1 and CK3 in self-test or scan-test mode.

[0153] The diagram 2200 shows one more timing scheme that can help faultdiagnosis as described in the description of FIG. 21. In the capturecycle 2208, two capture pulses of 150 MHz are applied to the captureclock CK1 711 and two capture pulses of 100 MHz are applied to thecapture clock CK3 717 while the other two capture clocks are heldinactive. As a result, for delay faults, only those in the clock domainCD1 702 and CD3 704 are detected. In addition, for stuck-at faults, onlythose in the crossing clock-domain logic blocks CCD1 706 to CCD3 708 andthe clock domains CD1 702 and CD3 703 are detected. Obviously, thisclock timing helps in fault diagnosis.

[0154]FIG. 23 shows a timing diagram of the full-scan design given inFIG. 1, in accordance with the present invention, where all captureclocks during the shift cycle are skewed to reduce power consumption.The timing diagram 2300 only shows the waveforms for the capture clocksCK1 111 to CK4 120 during the shift cycle. For the capture cycle, anycapture timing control methods claimed in this patent can be applied.

[0155] During the shift cycle 2305, clock pulses for the clocks CK1 111to CK4 120 are skewed by properly setting the delay 2301 between theshift pulses for the clocks CK1 111 and CK2 114, the delay 2302 betweenthe shift pulses for the clocks CK2 114 and CK3 117, the delay 2303between the shift pulses for the clocks CK3 117 and CK4 120, the delay2304 between the shift pulses for the clocks CK4 120 and CK1 111. As aresult, both peak power consumption and average power consumption arereduced. In addition, during the capture cycle, the PRPG 212 is drivenby clock CK2 114, the first-arrived capture clock, and the MISR 221 isdriven by clock CK3 117, the last-arrived capture clock, in the sharedPRPG-MISR pair 228 in FIG. 2. Thus, the ordered capture sequenceguarantees the correct capture operation when a shared PRPG-MISR pair isused for a plurality of clock domains in self-test mode.

[0156]FIG. 24 shows a flow chart of one embodiment of the invention. Themultiple-capture self-test computer-aided design (CAD) system 2400accepts the user-supplied HDL code or netlist 2402 together with theself-test control files 2401 and the chosen foundry library 2403. Theself-test control files 2401 contain all set-up information and scriptsrequired for compilation 2404, self-test rule check 2406, self-test rulerepair 2507, and multiple-capture self-test synthesis 2408. As a result,an equivalent combinational circuit model 2409 is generated. Then,combinational fault simulation 2410 can be performed. Finally,post-processing 2411 is used to produce the final self-test HDL code ornetlist 2412 as well as the HDL test benches and ATE test programs 2413.All reports and errors are saved in the report files 2414.

[0157] The multiple-capture self-test synthesis 2408 uses a hierarchicalapproach in which it synthesizes a plurality of PRPG-MISR pairs one at atime for each individual clock domain or combined clock domains, thensynthesizes a central self-test controller which includes an errorindicator, and finally stitches the central self-test controllertogether with synthesized PRPG-MISR pairs. Each PRPG-MISR pair iscomposed of a PRPG, an optional phase shifter, an optional spacecompactor, a MISR, and a comparator. In addition, during PRPG-MISRsynthesis, a number of spare scan cells can be inserted into selectedclock domains. As a result, the central self-test controller can remainintact even when the need for circuit modification rises at a laterstage.

[0158]FIG. 25 shows a flow chart of one embodiment of the invention. Themultiple-capture scan-test computer-aided design (CAD) system 2500accepts the user-supplied HDL code or netlist 2502 together with thescan control files 2501 and the chosen foundry library 2503. The scancontrol files 2501 contain all set-up information and scripts requiredfor compilation 2504, scan rule check 2506, scan rule repair 2507, andmultiple-capture scan synthesis 2508. As a result, an equivalentcombinational circuit model 2509 is generated. Then, combinational ATPG2510 can be performed. Finally, post-processing 2511 is used to producethe final scan HDL netlist 2512 as well as the HDL test benches and ATEtest programs 2513. All reports and errors are saved in the report files2514.

[0159] Having thus described presently preferred embodiments of thepresent invention, it can now be appreciated that the objectives of theinvention have been fully achieved. And it will be understood by thoseskilled in the art that many changes in construction & circuitry, andwidely differing embodiments & applications of the invention willsuggest themselves without departing from the spirit and scope of thepresent invention. The disclosures and the description herein areintended to be illustrative and are not in any sense limitation of theinvention, more preferably defined in the scope of the invention by theClaims appended hereto and their equivalents.

What is claimed is:
 1. A method for providing ordered capture clocks todetect or locate faults within N clock domains and faults crossing anytwo clock domains in an integrated circuit or circuit assembly inself-test mode, where N>1 and each domain has a plurality of scan cells,said method comprising the steps of: (a) generating and loading Npseudorandom stimuli to all said scan cells within said N clock domainsin said integrated circuit or circuit assembly during the shiftoperation; (b) applying an ordered sequence of capture clocks to allsaid scan cells within said N clock domains during the captureoperation; (c) compacting N output responses of all said scan cells tosignatures during the compact operation; and (d) repeating the steps of(a)-(c) until a predetermined limiting criteria is reached, wherein (a)and (c) occur substantially concurrently.
 2. The method of claim 1,wherein each said capture clock is programmable to contain one or moreclock pulses for performing said shift/compact and capture operations onall said scan cells within one said clock domain; wherein said clockdomain is solely controlled by said capture clock; and said captureclock can be either generated internally or controlled externally, andcan operate either at its rated clock speed (at-speed) or at a selectedclock speed.
 3. The method of claim 1, further comprising providing Nscan enable (SE) signals each within one said clock domain; wherein saidSE signals are used to switch operations from shift/compact to capture,and vice versa; and further said SE signals can be generated internallyor controlled externally, and are operated either at the rated clockspeeds (at-speed) or at selected clock speeds.
 4. The method of claim 3,wherein said providing N scan enable (SE) signals further comprisesusing one global scan enable (GSE) signal to drive said N scan enable(SE) signals; wherein said GSE signal is operated at a selected reducedclock speed.
 5. The method of claim 1, wherein said generating andloading N pseudorandom stimuli further comprises operating all captureclocks at selected clock speeds or at the same clock speed, and whenoperated at the same clock speed, all said capture clocks are skewed sothat at any given time only scan cells within one said clock domain arechanging states to reduce power consumption.
 6. The method of claim 1,further comprising the step of comparing said signatures with theirexpected signatures for error indication, after said predeterminedlimiting criteria is reached; wherein said step of comparing saidsignatures with their expected signatures further comprises comparingsaid signatures inside said integrated circuit or circuit assembly orshifting out said signatures for comparison in an ATE.
 7. The method ofclaim 1, wherein said generating and loading N pseudorandom stimulifurther comprises using a plurality of pseudorandom pattern generators(PRPGs) and phase shifters.
 8. The method of claim 7, wherein each saidpseudorandom pattern generator (PRPG) further comprises using afinite-state machine to automatically generate a number of testpatterns; wherein said test patterns are applied through a phase shifterto a plurality of clock domains.
 9. The method of claim 7, wherein eachsaid phase shifter further comprises using a combinational logic networkto decompress said test patterns to said pseudorandom stimuli.
 10. Themethod of claim 1, wherein said applying an ordered sequence of captureclocks further comprises performing said capture operation concurrentlyon a plurality of clock domains which do not have any logic blockcrossing each other.
 11. The method of claim 1, wherein said applying anordered sequence of capture clocks further comprises applying saidcapture clocks in a selected order for detecting or locating additionalfaults in said integrated circuit or circuit assembly.
 12. The method ofclaim 1, wherein said applying an ordered sequence of capture clocksfurther comprises applying another ordered sequence of capture clocksselectively longer or shorter than said ordered sequence of captureclocks for detecting or locating additional faults in said integratedcircuit or circuit assembly.
 13. The method of claim 1, wherein saidapplying an ordered sequence of capture clocks further comprisesdisabling one or more capture clocks to facilitate fault diagnosis. 14.The method of claim 1, wherein said applying an ordered sequence ofcapture clocks further comprises selectively operating said captureclock at a selected clock speed for detecting or locating stuck-atfaults within the clock domain controlled by said capture clock.
 15. Themethod of claim 1, wherein said applying an ordered sequence of captureclocks further comprises selectively operating said capture clock at itsrated clock speed for detecting or locating delay faults within theclock domain controlled by said capture clock.
 16. The method of claim1, wherein said applying an ordered sequence of capture clocks furthercomprises selectively reducing said capture clock speed to the levelwhere delay faults associated with all multiple-cycle paths of equalcycle latency within the clock domain are tested at a predeterminedrated clock speed.
 17. The method of claim 1, wherein said applying anordered sequence of capture clocks further comprises selectivelyoperating two said capture clocks at selected clock speeds for detectingor locating stuck-at faults crossing two said clock domains.
 18. Themethod of claim 1, wherein said applying an ordered sequence of captureclocks further comprises selectively adjusting the relative clock delayof two said capture clocks operating at selected clock speeds fordetecting or locating delay faults crossing two said clock domains. 19.The method of claim 1, wherein said applying an ordered sequence ofcapture clocks further comprises selectively adjusting the relativeclock delay of two said capture clocks to the level where delay faultsassociated with all multiple-cycle paths of equal cycle latency crossingtwo said clock domains are tested at a predetermined rated clock speed.20. The method of claim 1, wherein said applying an ordered sequence ofcapture clocks further comprises controlling the relative clock delaybetween any two adjacent capture clocks internally or external to saidintegrated circuit or circuit assembly.
 21. The method of claim 1,wherein said compacting N output responses further comprises using aplurality of space compactors and multiple-input signature registers(MISRs).
 22. The method of claim 21, wherein each said space compactorfurther comprises using a combinational logic network to compress saidoutput responses to compressed output responses.
 23. The method of claim21, wherein each said multiple-input signature register (MISR) furthercomprises using a finite-state machine to compact said compressed outputresponses to a signature; said MISR compacts said output responsesthrough a space compactor to said signature.
 24. The method of claim 1,further comprising using a PRPG-MISR pair to test faults within aplurality of clock domains when all capture clocks of said a pluralityof clock domains operate at the same clock speed; all said captureclocks are skewed so as to eliminate races and timing violation duringeach shift, capture, or compact operation.
 25. The method of claim 24,wherein said PRPG-MISR pair further comprises a PRPG, an optional phaseshifter, an optional space compactor, a MISR, and a comparator.
 26. Themethod of claim 25, wherein said PRPG-MISR pair further comprisesconnecting said PRPG to the first-arrived capture clock and connectingsaid MISR to the last-arrived capture clock within said a plurality ofclock domains.
 27. The method of claim 1, wherein said compacting Noutput responses further comprises selectively comparing said N outputresponses directly with their expected output responses and indicatingerrors immediately using a compare operation.
 28. The method of claim 1,wherein said scan cells are multiplexed D flip-flops or level sensitivelatches, and further wherein said integrated circuit or circuit assemblyunder test is a full-scan or partial-scan design.
 29. The method ofclaim 1, wherein said faults further comprise stuck-at faults and delayfaults; wherein said stuck-at faults further comprises other stuck-typefaults, such as open and bridging faults, and wherein said delay faultsfurther comprise other non-stuck-type delay faults, such as transition(gate-delay), multiple-cycle delay, and path-delay faults.
 30. Anapparatus for providing ordered capture clocks to detect or locatefaults within N clock domains and faults crossing any two clock domainsin an integrated circuit or circuit assembly in self-test mode, whereN>1 and each domain has a plurality of scan cells, said apparatuscomprising: (a) means for generating and loading N pseudorandom stimulito all said scan cells within said N clock domains in said integratedcircuit or circuit assembly during the shift operation; (b) means forapplying an ordered sequence of capture clocks to all said scan cellswithin said N clock domains during the capture operation; (c) means forcompacting N output responses of all said scan cells to signaturesduring the compact operation; and (d) means for repeating the steps of(a)-(c) until a predetermined limiting criteria is reached, wherein (a)and (c) occur substantially concurrently.
 31. The apparatus of claim 30,wherein said means of (a)-(d) are placed inside or external to saidintegrated circuit or circuit assembly.
 32. A method for providingordered capture clocks to detect or locate faults within N clock domainsand faults crossing any two clock domains in an integrated circuit orcircuit assembly in self-test mode, where N>1 and each domain has aplurality of scan cells, said method comprising the steps of: (a)shifting in N pseudorandom stimuli to all said scan cells within said Nclock domains in said integrated circuit or circuit assembly during theshift-in operation; (b) applying an ordered sequence of capture clocksto all said scan cells within said N clock domains during the captureoperation; and (c) shifting out N output responses of all said scancells for analysis during the shift-out operation.
 33. The method ofclaim 32, further comprising providing N scan enable (SE) signals eachwithin one said clock domain; wherein said SE signals are used to switchoperations from shift/compact to capture, and vice versa; and furthersaid SE signals can be generated internally or controlled externally,and are operated either at the rated clock speeds (at-speed) or atselected clock speeds.
 34. The method of claim 33, wherein saidproviding N scan enable (SE) signals further comprises using one globalscan enable (GSE) signal to drive said N scan enable (SE) signals;wherein said GSE signal is operated at a selected reduced clock speed.35. The method of claim 32, wherein said applying an ordered sequence ofcapture clocks further comprises any means for generating the orderedcapture sequence; wherein said ordered capture sequence does not includeany shift clock pulses during said capture operation.
 36. Acomputer-aided design (CAD) system for providing ordered capture clocksto detect or locate faults within N clock domains and faults crossingany two clock domains in an integrated circuit or circuit assembly inself-test mode, where N>1 and each domain has a plurality of scan cells,said CAD system comprising the computer-implemented steps of: (a)compiling the HDL code or netlist that represents said integratedcircuit or circuit assembly in physical form into a design database; (b)performing self-test rule check for checking whether said designdatabase contains any multiple-capture self-test rule violations; (c)performing self-test rule repair until all said multiple-captureself-test rule violations have been fixed; (d) performingmultiple-capture self-test synthesis for generating a self-test HDL codeor netlist; and (e) generating HDL test benches and ATE test programsfor verifying the correctness of said self-test HDL code or netlist. 37.The CAD system of claim 36, wherein said steps of (a)-(e) acceptuser-supplied self-test control information and report the results anderrors, if any.
 38. The CAD system of claim 36, wherein said performingself-test rule check further comprises determining the number of clockdomains and capture clocks required for self-test, the clock domains tobe tested concurrently, the ordered sequence of capture clocks to beapplied for self-test, and the capture clocks to be operated at therated clock speeds or at selected clock speeds.
 39. The CAD system ofclaim 36, wherein said performing multiple-capture self-test synthesisfurther comprises the hierarchical computer-implemented steps of: (a)synthesizing a plurality of PRPG-MISR pairs one at a time for eachindividual clock domain or combined clock domains, wherein each saidPRPG-MISR pair further comprises a PRPG, an optional phase shifter, anoptional space compactor, a MISR, and a comparator; (b) synthesizing acentral self-test controller which includes an error indicator; and (c)stitching said central self-test controller together with said PRPG-MISRpairs.
 40. The CAD system of claim 39, wherein said synthesizing aplurality of PRPG-MISR pairs domain-by-domain further comprisesinserting spare scan cells into selected clock domains.
 41. The CADsystem of claim 36, wherein said performing multiple-capture self-testsynthesis realizes said apparatus of claim 30 using said method ofclaim
 1. 42. The CAD system of claim 36, wherein said generating HDLtest benches and ATE test programs further comprises the steps oftransforming said design database into an equivalent combinationalcircuit model based on said ordered sequence of capture clocks, andperforming combinational fault simulation to compute the circuit'soutput responses, signatures, and fault coverage.
 43. A method forproviding ordered capture clocks to detect or locate faults within Nclock domains and faults crossing any two clock domains in an integratedcircuit or circuit assembly in scan-test mode, where N>1 and each domainhas a plurality of scan cells, said method comprising the steps of: (a)generating and loading N predetermined stimuli to all said scan cellswithin said N clock domains in said integrated circuit or circuitassembly during the shift operation; (b) applying an ordered sequence ofcapture clocks to all said scan cells within said N clock domains whereone or more capture clocks must contain two or more clock pulses duringthe capture operation; (c) comparing N output responses directly withtheir expected output responses for all said scan cells within said Nclock domains and indicating errors immediately during the compareoperation; and (d) repeating the steps of (a)-(c) until a predeterminedlimiting criteria is reached, wherein (a) and (c) occur substantiallyconcurrently.
 44. The method of claim 43, wherein each said captureclock is programmable to contain one or more clock pulses for performingsaid shift/compare and capture operations on all said scan cells withinone said clock domain; wherein said clock domain is solely controlled bysaid capture clock; and said capture clock can be either generatedinternally or controlled externally, and can operate either at its ratedclock speed (at-speed) or at a selected clock speed.
 45. The method ofclaim 43, further comprising providing N scan enable (SE) signals eachwithin one said clock domain; wherein said SE signals are used to switchoperations from shift/compact to capture, and vice versa; and furthersaid SE signals can be generated internally or controlled externally,and are operated either at the rated clock speeds (at-speed) or atselected clock speeds.
 46. The method of claim 45, wherein saidproviding N scan enable (SE) signals further comprises using one globalscan enable (GSE) signal to drive said N scan enable (SE) signals;wherein said GSE signal is operated at a selected reduced clock speed.47. The method of claim 43, wherein said generating and loading Npredetermined stimuli further comprises operating all capture clocks atselected clock speeds or at the same clock speed, and when operated atthe same clock speed, all said capture clocks are skewed so that at anygiven time only scan cells within one said clock domain are changingstates to reduce power consumption.
 48. The method of claim 43, whereinsaid applying an ordered sequence of capture clocks further comprisesperforming said capture operation concurrently on a plurality of clockdomains which do not have any logic block crossing each other.
 49. Themethod of claim 43, wherein said applying an ordered sequence of captureclocks further comprises applying said capture clocks in a selectedorder for detecting or locating additional faults in said integratedcircuit or circuit assembly.
 50. The method of claim 43, wherein saidapplying an ordered sequence of capture clocks further comprisesapplying another ordered sequence of capture clocks selectively longeror shorter than said ordered sequence of capture clocks for detecting orlocating additional faults in said integrated circuit or circuitassembly.
 51. The method of claim 43, wherein said applying an orderedsequence of capture clocks further comprises disabling one or morecapture clocks to facilitate fault diagnosis.
 52. The method of claim43, wherein said applying an ordered sequence of capture clocks furthercomprises selectively operating said capture clock at a selected clockspeed for detecting or locating stuck-at faults within the clock domaincontrolled by said capture clock.
 53. The method of claim 43, whereinsaid applying an ordered sequence of capture clocks further comprisesselectively operating said capture clock at its rated clock speed fordetecting or locating delay faults within the clock domain controlled bysaid capture clock.
 54. The method of claim 43, wherein said applying anordered sequence of capture clocks further comprises selectivelyreducing said capture clock speed to the level where delay faultsassociated with all multiple-cycle paths of equal cycle latency withinthe clock domain are tested at a predetermined rated clock speed. 55.The method of claim 43, wherein said applying an ordered sequence ofcapture clocks further comprises selectively operating two said captureclocks at selected clock speeds for detecting or locating stuck-atfaults crossing two said clock domains.
 56. The method of claim 43,wherein said applying an ordered sequence of capture clocks furthercomprises selectively adjusting the relative clock delay of two saidcapture clocks operating at selected clock speeds for detecting orlocating delay faults crossing two said clock domains.
 57. The method ofclaim 43, wherein said applying an ordered sequence of capture clocksfurther comprises selectively adjusting the relative clock delay of twosaid capture clocks to the level where delay faults associated with allmultiple-cycle paths of equal cycle latency crossing two said clockdomains are tested at a predetermined rated clock speed.
 58. The methodof claim 43, wherein said applying an ordered sequence of capture clocksfurther comprises controlling the relative clock delay between any twoadjacent capture clocks internally or external to said integratedcircuit or circuit assembly.
 59. The method of claim 43, wherein saidcomparing N output responses directly with their expected outputresponses further comprises selectively compacting said N outputresponses to signatures using a compact operation.
 60. The method ofclaim 59, wherein said compacting N output responses to signaturesfurther comprises comparing said signatures with their expectedsignatures after said predetermined limiting criteria is reached;wherein said comparing said signatures with their expected signaturesfurther comprises comparing said signatures inside said integratedcircuit or shifting out said signatures for comparison in an ATE. 61.The method of claim 43, wherein said scan cells are multiplexed Dflip-flops or level sensitive latches, and further wherein saidintegrated circuit or circuit assembly under test is a full-scan orpartial-scan design.
 62. The method of claim 43, wherein said faultsfurther comprise stuck-at faults and delay faults; wherein said stuck-atfaults further comprises other stuck-type faults, such as open andbridging faults, and wherein said delay faults further comprises othernon-stuck-type delay faults, such as transition (gate-delay),multiple-cycle delay, and path-delay faults.
 63. An apparatus forproviding ordered capture clocks to detect or locate faults within Nclock domains and faults crossing any two clock domains in an integratedcircuit or circuit assembly in scan-test mode, where N>1 and each domainhas a plurality of scan cells, said apparatus comprising: (a) means forgenerating and loading N predetermined stimuli to all said scan cellswithin said N clock domains in said integrated circuit or circuitassembly during the shift operation; (b) means for applying an orderedsequence of capture clocks to all said scan cells within said N clockdomains where one or more capture clocks must contain two or more clockpulses during the capture operation; (c) means for comparing N outputresponses directly with their expected output responses for all saidscan cells within said N clock domains and indicating errors immediatelyduring the compare operation; and (d) means for repeating the steps of(a)-(c) until a predetermined limiting criteria is reached, wherein (a)and (c) occur substantially concurrently.
 64. The apparatus of claim 63,wherein said means of (a)-(d) are placed inside or external to saidintegrated circuit or circuit assembly.
 65. A method for providingordered capture clocks to detect or locate faults within N clock domainsand faults crossing any two clock domains in an integrated circuit orcircuit assembly in scan-test mode, where N>1 and each domain has aplurality of scan cells, said method comprising the steps of: (a)shifting in N predetermined stimuli to all said scan cells within said Nclock domains in said integrated circuit or circuit assembly during theshift-in operation; (b) applying an ordered sequence of capture clocksto all said scan cells within said N clock domains where one or morecapture clocks must contain two or more clock pulses during the captureoperation; and (c) shifting out N output responses of all said scancells for analysis during the shift-out operation.
 66. The method ofclaim 65, further comprising providing N scan enable (SE) signals eachwithin one said clock domain; wherein said SE signals are used to switchoperations from shift/compact to capture, and vice versa; and furthersaid SE signals can be generated internally or controlled externally,and are operated either at the rated clock speeds (at-speed) or atselected clock speeds.
 67. The method of claim 66, wherein saidproviding N scan enable (SE) signals further comprises using one globalscan enable (GSE) signal to drive said N scan enable (SE) signals;wherein said GSE signal is operated at a selected reduced clock speed.68. The method of claim 65, wherein said applying an ordered sequence ofcapture clocks further comprises any means for generating the orderedcapture sequence; wherein said ordered capture sequence does not includeany shift clock pulses during said capture operation.
 69. Acomputer-aided design (CAD) system for providing ordered capture clocksto detect or locate faults within N clock domains and faults crossingany two clock domains in an integrated circuit or circuit assembly inscan-test mode, where N>1 and each domain has a plurality of scan cells,said CAD system comprising the computer-implemented steps of: (a)compiling the HDL code or netlist that represents said integratedcircuit or circuit assembly in physical form into a design database; (b)performing scan rule check for checking whether said design databasecontains any multiple-capture scan rule violations; (c) performing scanrule repair until all said multiple-capture scan rule violations havebeen fixed; (d) performing multiple-capture scan synthesis forgenerating a scan HDL netlist; and (e) generating HDL test benches andATE test programs, where one or more capture clocks must contain two ormore clock pulses, for verifying the correctness of said scan HDLnetlist.
 70. The CAD system of claim 69, wherein said steps of (a)-(e)accept user-supplied scan control information and report the results anderrors, if any.
 71. The CAD system of claim 69, wherein said performingscan rule check further comprises determining the number of clockdomains and capture clocks required for scan-test, the clock domains tobe tested concurrently, the ordered sequence of capture clocks to beapplied for scan-test, and the capture clocks to be operated at therated clock speeds or at selected clock speeds.
 72. The CAD system ofclaim 69, wherein said performing multiple-capture scan synthesisfurther comprises inserting spare scan cells into selected clockdomains.
 73. The CAD system of claim 69, wherein said performingmultiple-capture scan synthesis realizes said apparatus of claim 63using said method of claim
 43. 74. The CAD system of claim 69, whereinsaid generating HDL test benches and ATE test programs further comprisesthe steps of transforming said design database into an equivalentcombinational circuit model based on said ordered sequence of captureclocks, and performing combinational ATPG to generate the circuit's testpatterns and report its fault coverage.
 75. The CAD system of claim 69,wherein said generating HDL test benches and ATE test programs furthercomprises performing combinational logic simulation on saidcombinational circuit model to compute said circuit's signatures when acompact operation is employed to compact said circuit's outputresponses.